Application Fee
- Registration Fee of Rs. 500/- per position
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NIELIT Recruitment 2025 Important Dates
- Last Date for Apply: 25-07-2025
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NIELIT Recruitment Notification 2025 Age Limit (as on 25-07-2025)
- Maximum Age limit: 50 Years
- Age relaxation is applicable as per rules.
- Age limit for Assistant Professor: Up to 50 Years
- Age limit for Associate Professor: Up to 50 Years
- Age limit for Professor: Up to 50 Years
- Age limit for Team Lead: Up to 50 Years
- Age limit for VLSI Design Expert/ Junior VLSI Engineer: Up to 45 Years
- Age limit for Senior Trainers (VLSI Design)/ Senior VLSI Engineer: Up to 50 Years
- Age limit for Team Leader (Platform Development Team): Up to 45 Years
- Age limit for DevOps Engineer: Up to 40 Years
- Age limit for Full Stack Engineer: Up to 45 Years
- Age limit for Graphics Designer: Up to 45 Years
- Age limit for Sr. Resource Person: Up to 50 Years
- Age limit for Consultant (Design Verification & EDA Integration): Up to 50 Years
- Age limit for Senior Resource Person (Project Officer): Up to 50 Years
- Age limit for Resource Person: Up to 50 Years
- Age limit for Consultant: Up to 40 Years
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Qualification
- Candidates Should Posses Graduate, B.Sc, B.Tech/ B.E, Masters Degree, M.E/ M.Tech, MCA, M.Phil/ Ph.D (Relevant fields).
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Salary
- Assistant Professor: Rs. 60,000/- to Rs. 70,000/- P.M
- Associate Professor: Rs. 80,000/- to Rs. 90,000/- P.M
- Professor: Rs. 90,000/- to Rs. 1,00,000/- P.M
- Team Lead: Rs. 95,000/- P. M.
- VLSI Design Expert/ Junior VLSI Engineer: Rs. 40,000/- P.M
- Senior Trainers (VLSI Design)/ Senior VLSI Engineer: Rs. 65000/- P.M
- Team Leader (Platform Development Team): Rs. 95,000/- P.M
- DevOps Engineer: Rs. 65,000/- P.M
- Full Stack Engineer: Rs. 65,000/- P.M
- Graphics Designer: Rs. 40000/- P.M
- Sr. Resource Person: Rs. 60000/- P.M
- Consultant (Design Verification & EDA Integration): Rs. 2.50 Lakhs /- P.M
- Senior Resource Person (Project Officer): Rs. 60,000/- to 80000/- P.M
- Resource Person: Rs. 67,700/- P. M.
- Consultant: Rs. 70,000/-
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NIELIT Recruitment 2025 Vacancy Details
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Post Name |
Total |
Assistant Professor |
28 |
Associate Professor |
13 |
Professor |
06 |
Team Lead (VLSI Design) |
05 |
VLSI Design Expert/ Junior VLSI Engineer |
10 |
Senior Trainers (VLSI Design)/ Senior VLSI Engineer |
04 |
Team Leader (Platform Development Team) |
01 |
DevOps Engineer |
04 |
Full Stack Engineer |
06 |
Graphics Designer |
01 |
Sr. Resource Person |
01 |
Consultant (Design Verification & EDA Integration) |
01 |
Senior Resource Person (Project Officer) |
01 |
Resource Person |
01 |
Consultant |
01 |
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Important Links |
Notification |
Click here |
Official Website |
Click here |